Normally-off integrated JFET power switches in wide bandgap semiconductors and methods of making

ABSTRACT

Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single- or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant electronics components. Methods of making the devices are also described.

This application is related to U.S. Patent Application No. 60/585,881, filed Jul. 8, 2004, and U.S. patent application Ser. No. ______, entitled: “Lateral Trench Field-Effect Transistors in Wide Bandgap Semiconductor Materials, Methods of Making, And Integrated Circuits Incorporating the Transistors”, filed on even date herewith. Each of the aforementioned applications is incorporated by reference herein in its entirety.

BACKGROUND

1. Technical Field

The present invention relates generally to field effect transistors (FETs), and in particular, to such transistors formed in wide bandgap semiconductor materials. Further, this invention relates to monolithic and hybrid integrated circuits comprising low-voltage control circuitry and to power switches built using the above transistors.

2. Background of the Technology

Wide bandgap semiconductor materials (with E_(G)>2 eV) such as silicon carbide (SiC) or Group III nitride compound semiconductors (e.g., gallium nitride or GaN) are very attractive for use in high-power, high-temperature, and/or radiation resistant electronics. Monolithic or hybrid integration of a power

a drift layer of an n-type semiconductor material on and non-coextensive with the drain layer such that portions of the drain layer are exposed, the drift layer having a lower conductivity than the drain layer;

one or more raised regions comprising a channel region of an n-type semiconductor material on the drift layer and a source region of an n-type semiconductor material on the channel region, the material of the source region having a higher conductivity than that of the channel region;

a gate region of a p-type semiconductor material on the drift layer adjacent the one or more raised regions and forming a rectifying junction with the drift layer and the channel region(s);

ohmic contacts the gate and source regions and on exposed portions of the drain layer;

a second vertical channel JFET discrete from the first vertical channel JFET comprising:

a substrate of an n-type semiconductor material having opposed first and second major surfaces;

a drain layer of an n-type semiconductor material on the first major surface of the substrate;

a drift layer of an n-type semiconductor material on the drain layer, the drift layer having a lower conductivity than the drain layer;

one or more raised regions comprising a channel region of an n-type semiconductor material on the drift layer and a source region of an n-type semiconductor material on the channel region, the material of the source region having a higher conductivity than that of the channel region;

transistor and control circuitry in a single or multi-chip wide bandgap power semiconductor module is highly desirable for such applications in order to improve the efficiency and reliability of the system.

SiC smart power technology has been a topic of discussion in recent years, but has experienced limited scientific investigation. Proposed solutions have been met with skepticism relating to the operation of both the power switch and control circuitry.

Because of the fundamental differences in material properties and processing technologies, traditional Si or GaAs integrated circuit (IC) technologies such as Complementary Metal-Oxide-Semiconductor (CMOS) or Direct Coupled FET Logic (DCFL) cannot in most cases be easily transferred to wide bandgap semiconductors. Several attempts at fabricating SiC NMOS and CMOS digital and analog ICs have been reported in the last decade (e.g., [1], [2]). A monolithic CMOS integrated device in SiC and method of fabricating the same is disclosed in U.S. Pat. No. 6,344,663, [3]. Moreover, recent development in SiC Lateral DMOS Field-Effect Transistors (LDMOSFETs) (e.g., [4]-[5]) theoretically allow for the monolithic integration of MOSFET-based control circuitry and power switches for use in Smart Power electronics. Various issues, however, limit the use of MOSFET-based SiC integrated circuits in the applications where high-temperature and/or radiation tolerance is required. The first such issue is on-state insulator reliability as a result of a much smaller conduction band offset of SiC to SiO₂ as compared to that of silicon. This issue becomes even more significant at high temperatures and in extreme radiation environments. Other issues include: low inversion channel mobility due to high interface state density at the SiC/SiO₂ interface and high fixed charge density in the insulator; and significant threshold voltage shift with temperature due to ionization of interface states.

Another transistor candidate for use in SiC Smart Power electronics, a SiC bipolar junction transistor (BJT), also suffers from interface-related issues such as high recombination velocity on the surface between the emitter and the base resulting in low current gain and high control losses.

Another transistor candidate for use in SiC Smart Power electronics is a Metal Semiconductor Field-Effect Transistor (MESFET). Despite the fact the SiC MESFET monolithic microwave integrated circuits (MMICs) received significant development in the last decade (e.g., [6]), there have been few published attempts to build SiC MESFET logic and analog circuits (e.g., [7]).

An alternative to the MOSFET and MESFET approaches is the use of lateral JFET-based integrated circuits implemented in either complementary (n-type and p-type channels as disclosed in U.S. Pat. No. 6,503,782 [8]) or enhanced-depletion (n-type channels) forms. SiC JFETs have proven to be radiation tolerant while demonstrating very insignificant threshold voltage shift with temperature. Encouraging results in the development of high-temperature normally-on power vertical junction field-effect transistors (VJFETs) have been published in recent years (e.g., [9]). However, despite their excellent current-conduction and voltage-blocking capabilities, a major deficiency of these transistors is that they are “normally-on” devices. On the system level, this often requires an additional (negative) supply voltage and short circuit protection.

Several attempts to build normally-off SiC high-voltage VJFET switches have been reported recently. Typically, these devices comprise both lateral and vertical channel regions (e.g., [10]-[12]). These devices, however, exhibit a drastic contradiction between the device blocking capabilities and the specific on-resistance. For example, a VJFET with a 75 μm, 7×10⁴ cm⁻³ n-type drift region was able to block above 5.5 kV at zero gate-to-source voltage [13]. At the same time, this device demonstrated a specific on-resistance (R_(sp-on)) of more then 200 mΩ*cm³. The intrinsic resistance of its drift layer estimated from its thickness and doping was slightly above 60 mΩ*cm³, with the remainder of the on-resistance was contributed by the channel regions.

In order to reduce the specific on-resistance of SiC power VJFETs, these devices can be driven in bipolar mode by applying high positive gate-to-source voltage. For example, the device discussed above and disclosed in [13] demonstrated an R_(sp-on) of 66.7 mΩ*cm³ when a gate-to-source bias of 5 V was applied [14]. This approach, however, can lead to significant power losses due to high gate current.

Another approach is to use special circuits and methods for controlling normally-on devices so that they can be operated in normally-off mode. A cascode connection of a low-voltage control JFET with a high-voltage JFET wherein the drain of the control JFET is connected to the source of the high-voltage device and the gate of high-voltage JFET is connected to the source of the control JFET has been disclosed in U.S. Pat. No. 3,767,946 [15]. A compound field-effect transistor monolithically implementing such a cascode connection has also been disclosed in U.S. Pat. No. 4,107,725 [16]. Similar types of cascode circuits, where low-voltage normally-off devices control high-voltage normally-on devices are disclosed in U.S. Pat. No. 4,663,547 [17]. More recently, a normally-on SiC VJFET controlled by an Si MOSFET in the above configuration has been reported by several groups (e.g., [18]). This integrated power switch has demonstrated excellent voltage-blocking and current-conducting capabilities, as well as high switching speed. However, the use of silicon MOSFETs for the control of power in normally-on SiC VJFETs significantly limits both the temperature range and the radiation tolerance of the cascode. Accordingly, there is still a need for wide bandgap normally-off power switching device in general, and in particular, for such a power switch integrated with control circuitry built in wide bandgap semiconductors.

SUMMARY

According to a first embodiment, a monolithic integrated circuit is provided which comprises:

a substrate having opposed first and second major surfaces; and

first and second junction field-effect transistors on discrete locations on the first major surface of the substrate, each of the first and second junction field-effect transistors comprising:

a drain layer of an n-type semiconductor material on and non-coextensive with the first major surface of the substrate such that portions of the substrate surrounding the drain layer are exposed;

a drift layer of an n-type semiconductor material on and non-coextensive with the drain layer such that portions of the drain layer are exposed, the drift layer having a lower conductivity than the drain layer;

one or more raised regions on discrete locations on the drift layer, each raised region comprising a channel region of an n-type semiconductor material on the drift layer and a source region of an n-type semiconductor material on the channel region, the semiconductor material of the source region having a higher conductivity than that of the channel region;

a gate region of a p-type semiconductor material on the drift layer adjacent the one or more raised regions and forming a rectifying junction with n-type material of the drift layer and the channel region(s);

ohmic contacts on the gate and source regions and on exposed portions of the drain layer;

a first electrical connection between the source ohmic contact of the first junction field-effect transistor and the gate ohmic contact of the second junction field-effect transistor; and

a second electrical connection between the drain ohmic contact of the first junction field-effect transistor and the source ohmic contact of the second junction field-effect transistor.

According to a second embodiment, a monolithic integrated circuit is provided which comprises:

a substrate having opposed first and second major surfaces; and

a buffer layer of a p-type semiconductor material on the first major surface of the substrate;

first and second discrete channel regions each of an n-type semiconductor material in spaced relation on the buffer layer, the second channel region comprising a base portion on the buffer layer and an upper portion, the base portion extending laterally beyond the upper portion so as to form a shoulder;

a source region of an n-type semiconductor material on the buffer layer adjacent to and in contact with the first channel region;

a source/drain region of an n-type semiconductor material on the buffer layer between the first channel region and the second channel region and in contact with both the first channel region and the second channel region, a portion of the source/drain region overlapping the shoulder portion of the second channel region;

a drain region on the shoulder of the second channel region such that the drain region does not directly contact the buffer layer;

a first gate region of a p-type semiconductor material on the first channel region and forming a rectifying junction therewith;

a second gate region of a p-type semiconductor material on an upper surface of the top portion of the second channel region and forming a rectifying junction therewith; and

ohmic contacts on the source region, the first and second gate regions, the source/drain region and the drain region.

According to a third embodiment, an integrated circuit is provided which comprises:

a first vertical channel JFET comprising:

a substrate having opposed first and second surfaces;

a drain layer of an n-type semiconductor material on the first surface of the substrate;

a gate region of a p-type semiconductor material on the drift layer adjacent the one or more raised regions and forming a rectifying junction with the drift layer and the channel region(s); and

ohmic contacts on the gate and source regions and on the second major surface of the substrate;

a first electrical connection between the drain ohmic contact of the first vertical channel JFET and the source ohmic contact of the second vertical channel JFET; and

a second electrical connection between the source ohmic contact of the first vertical channel JFET and the gate ohmic contact of the second vertical channel JFET.

According to a fourth embodiment, an integrated circuit is provided which comprises:

a discrete lateral channel JFET comprising:

a substrate having opposed first and second major surfaces;

a buffer layer of a p-type semiconductor material on the first major surface of the substrate;

discrete source and drain regions each of an n-type semiconductor material in spaced relation on the buffer layer;

a channel region of an n-type semiconductor material on the buffer layer between the source and drain regions and in contact with each of the source and drain regions;

a gate region of a p-type semiconductor material on the channel region and forming a rectifying junction therewith;

ohmic contacts on the source, gate, and drain regions;

a discrete vertical channel JFET comprising:

a substrate of an n-type semiconductor material having opposed first and second major surfaces;

a drain layer of an n-type semiconductor material on the first major surface of the substrate;

a drift layer of an n-type semiconductor material on the drain layer, the drift layer having a lower conductivity than the drain layer;

one or more discrete raised regions each comprising a channel region of an n-type semiconductor material on the drift layer and a source region of an n-type semiconductor material on the channel region, the material of the source region having a higher conductivity than that of the channel region;

a gate region of a p-type semiconductor material on the drift layer adjacent the one or more raised regions and forming a rectifying junction with the drift layer and the channel region(s); and

ohmic contacts on the gate and source regions and on the second major surface of the substrate;

a first electrical connection between the drain ohmic contact of the lateral channel JFET and the source ohmic contact of the vertical channel JFET; and

a second electrical connection between the source ohmic contact of the lateral channel JFET and the gate ohmic contact of the vertical channel JFET.

According to a fifth embodiment, a monolithic lateral channel junction field-effect transistor (JFET) is provided which comprises:

a substrate having opposed first and second major surfaces; and

a buffer layer of a p-type semiconductor material on the first major surface of the substrate;

a channel layer of an n-type semiconductor material on the buffer layer;

discrete source and drain regions of an n-type semiconductor material in spaced relation on the channel layer;

a source/drain region of an n-type semiconductor material on the channel layer between the source and drain regions and spaced from each of the source and drain regions;

a first gate region of a p-type semiconductor material formed in the channel layer between the source and source/drain regions and forming a rectifying junction with the channel layer;

a second gate region of a p-type semiconductor material formed in the channel layer between the source/drain and drain regions and forming a rectifying junction with the channel layer;

ohmic contacts on the source region, the first and second gate regions, the source/drain region and the drain region.

According to a sixth embodiment, an integrated circuit is provided which comprises:

a discrete lateral channel JFET comprising:

a substrate having opposed first and second major surfaces; and

a buffer layer of a p-type semiconductor material on the first surface of the substrate;

a channel layer of an n-type semiconductor material on the buffer layer;

discrete source and drain regions of an n-type semiconductor material in spaced relation on the channel layer;

a gate region of a p-type semiconductor material formed in the channel layer between the source and drain regions and forming a rectifying junction with the channel layer;

ohmic contacts on the source region, the gate region, and the drain region;

a discrete vertical channel JFET comprising:

a substrate of an n-type semiconductor material having opposed first and second major surfaces;

a drain layer of an n-type semiconductor material on the first major surface of the substrate;

a drift layer of an n-type semiconductor material on the drain layer, the drift layer having a lower conductivity than the drain layer;

one or more discrete raised regions each comprising a channel region of an n-type semiconductor material on the drift layer and a source region of an n-type semiconductor material on the channel region, the material of the source region having a higher conductivity than that of the channel region;

a gate region of a p-type semiconductor material on the drift layer adjacent the one or more raised regions and forming a rectifying junction with the drift layer and the channel region(s); and

ohmic contacts on the gate and source regions and on the second major surface of the substrate;

a first electrical connection between the source ohmic contact of the lateral channel JFET and the gate ohmic contact of the vertical channel JFET; and

a second electrical connection between the drain ohmic contact of the lateral channel JFET and the source ohmic contact of the vertical channel JFET.

According to a seventh embodiment, a monolithic integrated circuit is provided which comprises a lateral junction field effect transistor and a vertical junction field effect transistor;

the lateral junction field effect transistor comprising:

a buffer layer of a p-type semiconductor material formed in a portion of a first major surface of a drift layer;

a channel layer of an n-type semiconductor material on and non-coextensive with the buffer layer such that a portion of the buffer layer is exposed;

discrete source and drain regions of an n-type semiconductor material in spaced relation on the channel layer;

a gate region of a p-type semiconductor material formed in the channel layer between the source and drain regions and forming a rectifying junction with the channel layer;

ohmic contacts on the source region, the gate region, the drain region and on the exposed portion of the buffer layer; the vertical junction field effect transistor comprising:

a channel layer of an n-type semiconductor material on the first major surface of the drift layer laterally spaced from the buffer layer;

one or more discrete source regions of an n-type semiconductor material in spaced relation on the channel layer;

a gate region of a p-type semiconductor material formed in the channel layer adjacent the one or more source regions and forming a rectifying junction with the channel layer; and

ohmic contacts on the gate and source regions;

wherein the drift layer is on a drain layer of an n-type semiconductor material which is on a first major surface of a substrate; and wherein an electrical contact is on a second major surface of the substrate opposite the first major surface of the substrate.

According to an eighth embodiment, a monolithic integrated circuit is provided which comprises a lateral junction field effect transistor and a vertical junction field effect transistor;

the lateral junction field effect transistor comprising:

a buffer layer of a p-type semiconductor material formed in a portion of a first major surface of a drift layer;

a channel layer of an n-type semiconductor material on and non-coextensive with the buffer layer such that a portion of the buffer layer is exposed;

discrete source and drain regions each of an n-type semiconductor material in spaced relation on the channel layer;

a metal layer on the channel layer between the source and drain regions forming a metal-semiconductor rectifying junction with the channel layer;

ohmic contacts on the source region, the drain region and on the exposed portion of the buffer layer;

the vertical junction field effect transistor comprising:

one or more raised regions on the first major surface of the drift layer laterally spaced from the buffer layer each comprising a channel region of an n-type semiconductor material on the first major surface of the drift layer and spaced from the buffer layer of the lateral junction field effect transistor and a source region of an n-type semiconductor material on the channel region;

a metal layer on the drift layer adjacent to the one or more raised regions forming a metal-semiconductor rectifying junction with the drift layer and the channel region(s); and

an ohmic contact on the source region;

wherein the drift layer is on a layer of n-type semiconductor material which is on a first major surface of a substrate; and wherein an electrical contact is on a second major surface of the substrate opposite the first major surface of the substrate.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a schematic cross-section of a monolithic inverter circuit comprising enhanced and depletion mode LTJFETs.

FIG. 2 is a schematic cross-section of a monolithic normally-off JFET comprising enhanced and depletion mode LTJFETs having a built-in PiN diode.

FIGS. 3A and 3B are a circuit representation (FIG. 3A) and an example layout (FIG. 3B) of a monolithic normally-off JFET integrated circuit comprising enhanced and depletion mode LTJFETs having a built-in PiN diode.

FIG. 4 is a schematic cross-sectional representation of a monolithic normally-off JFET built using enhanced and depletion mode LTJFETs integrated with an SBD or a JBS diode.

FIGS. 5A and 5B are a circuit representation (FIG. 5A) and an example layout (FIG. 5B) of a monolithic normally-off JFET integrated circuit comprising enhanced and depletion mode LTJFETs integrated with an SBD or a JBS diode.

FIG. 6 is a schematic cross-sectional representation of a hybrid normally-off JFET built using an enhanced mode LTJFET and a depletion mode VJFET having a built-in PiN diode.

FIG. 7 is a schematic cross-sectional representation of a hybrid normally-off JFET built using enhanced mode LTJFETs and a depletion mode VJFET integrated with an SBD or a JBS diode.

FIG. 8 is a circuit representation of a monolithic LTJFET timer circuit driving a built-on-chip low-voltage high-current enhanced-mode LTJFET connected in cascode with a discrete high-voltage normally-on power VJFET.

FIG. 9 is a schematic cross-sectional representation of a monolithic inverter circuit built using enhanced and depletion mode overgrown-gate LJFETs.

FIG. 10 is a schematic cross-sectional representation of a hybrid normally-off JFET comprising an enhanced mode overgrown-gate LJFET and a depletion mode VJFET.

FIG. 11 is a schematic cross-sectional representation of a hybrid normally-off JFET power-switch comprising a low voltage enhanced mode LJFET and a high voltage discrete normally-on depletion mode VJFET.

FIG. 12 is a schematic cross-sectional representation of a monolithic inverter circuit built using enhanced and depletion mode implanted-gate LJFETs.

FIG. 13 is a schematic cross-sectional representation of a monolithic normally-off JFET integrated circuit built using enhanced and depletion mode implanted-gate LJFETs.

FIG. 14 is a schematic cross-sectional representation of hybrid normally-off JFET integrated circuit built using an enhanced mode implanted-gate LJFET and a depletion mode VJFET.

FIG. 15 is a schematic cross-sectional representation of a hybrid normally-off JFET integrated circuit built using an enhanced mode dual-gate LJFET and a depletion mode VJFET wherein the bottom gate of the LJFET is implanted into the drift region.

FIG. 16 is a schematic cross-sectional representation of a hybrid guard-ring terminated normally-off JFET integrated circuit built using an enhanced mode dual-gate LJFET and a depletion mode VJFET wherein the bottom gate of the LJFET and the guard rings are implanted into the drift region.

FIG. 17 is a schematic cross-sectional representation of a hybrid guard-ring terminated normally-off JFET built using an enhanced mode dual-gate LJFET and a depletion mode VJFET with a Schottky gate wherein the bottom gate of the LJFET and the guard rings are implanted into the drift region.

FIGS. 18A-18D are a simulated device structure (FIG. 18A), schematic cross sectional representation (FIG. 18B) and graphs showing the output DC characteristics (FIGS. 18C and 18D) of a SiC LTJFET integrated switch.

FIGS. 19A-19D are a photograph (FIG. 19A), circuit representation (FIG. 19B) and graphs (FIGS. 19C and 19D) showing measured characteristics of a hybrid normally-off 900 V power switch.

FIGS. 20A and 20B are a circuit representation (FIG. 20A) and a graph (FIG. 20B) showing measured internal voltages of a hybrid normally-off, 900 V power switch.

FIGS. 21A-21C are schematic representations of distributed drain resistances of an LTJFET (FIG. 21A) and a VJFET (FIG. 21B) along with a graph (FIG. 21C) showing the resistance of the lateral drain layer of an LTJFET normalized to the resistance of the vertical drain of a VJFET as a function of finger length for different doping levels of the lateral drain layer.

FIGS. 22A-22H illustrate a method of making a monolithic integrated circuit as set forth in FIGS. 9 and 10.

FIGS. 23A-23H illustrate a method of making a monolithic integrated circuit as set forth in FIGS. 12 and 13.

FIGS. 24A-24J illustrate a method of making a monolithic integrated circuit as set forth in FIG. 15.

FIGS. 25A-25D illustrate a method of making a monolithic integrated circuit as set forth in FIG. 17.

REFERENCE NUMERALS

The reference numerals used in the drawings are defined as set forth below. For the substrate, implanted regions, and epitaxially grown layers, representative thicknesses and doping concentrations are also provided. # Material 1 Substrate (e.g., semi-insulating substrate) 1a N-type substrate (e.g., doping level >1 × 10¹⁸ cm⁻³) 2 Epitaxially grown layer (p-type) (e.g., ≧0.1 μm thick, 1 × 10¹⁵-1 × 10¹⁷ cm⁻³) 3 Epitaxially grown layer (n-type) (e.g., 0.2-5 μm, >5 × 10¹⁸ cm⁻³) 3a Epitaxially grown layer (n-type) (e.g., 0.5-1 μm, >5 × 10¹⁸ cm⁻³) 4 Epitaxially grown layer (n-type) (e.g., 0.5-10 μm 5 × 10¹⁵- 5 × 10¹⁷ cm⁻³) 4a Epitaxially grown layer (n-type) (e.g., 5-350 μm, 2 × 10¹⁴- 2 × 10¹⁶ cm⁻³) 5 Epitaxially grown layer (n-type) (e.g., 0.2-1.5 μm, 5 × 10¹⁵- 5 × 10¹⁷ cm⁻³ 5a Epitaxially grown layer (n-type) (e.g., 0.2-1.5 μm, 5 × 10¹⁵- 2 × 10¹⁷ cm⁻³) 5b Epitaxially grown layer (n-type) (e.g., 0.3-1.5 μm, 5 × 10¹⁵- 2 × 10¹⁷ cm⁻³) 6 Epitaxially grown layer (n-type) (e.g., 0.2-1.5 μm, >5 × 10¹⁸ cm⁻³) 6a Implanted region (n-type) (e.g., ≧0.1 μm, ≧5 × 10¹⁸ cm⁻³) 7 Implanted region (p-type) (e.g., ≧0.1 μm ≧5 × 10¹⁸ cm⁻³) 7a Epitaxially grown layer (p-type) (e.g., 0.2-1.5 μm, >5 × 10¹⁸ cm⁻³) 8 Ohmic contact 9 Schottky contact

DETAILED DESCRIPTION

The present invention will be described in more detail hereafter with reference to the accompanying drawings and photographs, in which preferred embodiments of the invention are described with silicon carbide (SiC) semiconductor serving as an example.

Silicon carbide crystallizes in numerous (i.e., more than 200) different modifications (polytypes). The most important are: 3C—SiC (cubic unit cell, zincblende); 2H—SiC; 4H—SiC; 6H—SiC (hexagonal unit cell, wurtzile); 15R—SiC (rhombohedral unit cell). The 4H polytype is more attractive for power devices, because of its higher electron mobility. Although the 4H—SiC is preferred, it is to be understood that the present invention is applicable to devices and integrated circuits described herein made of other wide bandgap semiconductor materials such as gallium nitride, and other polytypes of silicon carbide, by way of example.

FIG. 1 shows a schematic cross-section of enhanced and depletion mode semiconductor devices referred to a Lateral Trench Junction Field-Effect Transistors (LTJFETs), and a schematic presentation of electrical connections used to form a monolithic inverter circuit. As shown, the devices used to form the inverter are built on a wide bandgap semiconductor substrate (1), which can be either: semi-insulating; p-type; or n-type with a p-type buffer layer. As shown in FIG. 1, the devices comprise drain (3), drift (4), channel (5), and source (6) expitaxially grown n-type layers, and p-type implanted gate regions (7). The device structures can be defined using plasma etching and ion implantation. In the circuit shown in FIG. 1, the ohmic contacts to the source, gate, and drain regions can be formed on the same side of the wafer, which allows for the devices to be used in monolithic integrated circuits. A complete description of a device as described above and shown in FIG. 1 as well as an exemplary fabrication method for this device can be found in U.S. patent application Ser. No. ______, entitled: “Lateral Trench Field-Effect Transistors in Wide Bandgap Semiconductor Materials, methods of Making, and Integrated Circuits Incorporating the Transistors”, filed on even date herewith, which application is incorporated by reference herein in its entirety.

FIG. 2 is a schematic representation of a monolithic normally-off JFET comprising single-finger enhanced and depletion mode LTJFETs and having a built-in PiN diode. A schematic presentation of electrical connections is also shown in FIG. 2. As shown in FIG. 2, the devices are connected in cascode configuration in such a way that the drain of the enhanced mode transistor (referred to as an “EJFET”) is connected to the source of the depletion mode transistor (referred to as a “DJFET”), and the gate of the DJFET is connected to the source of the control EJFET. The p-n junctions formed in between the gate regions (7) and the drift layer (4) of the DJFET of this device form a so called anti-parallel free-wheeling PiN diode. The size of this diode can be defined by the widths of implanted gate regions.

Although FIG. 2 shows single-finger device implementation of a normally-off JFET, in practice multi-finger LTJFETs can be used to form power switches. FIGS. 3A and 3B shows a schematic circuit representation (FIG. 3A) and an exemplary layout design (FIG. 3B) of a monolithic multi-finger normally-off power switch.

In order to reduce switching losses, the PiN diode shown as in FIGS. 3A and 3B can be replaced with a Schottky Barrier diode (SBD) or a Junction Barrier Schottky (JBS) diode. Methods of forming Schottky gates in a trench structure are disclosed in U.S. Patent Application No. 60/585,881, filed Jul. 8, 2004, which application is incorporated by reference herein in its entirety. FIG. 4 provides a schematic cross-section of a monolithic normally-off JFET power switch with an integrated free-wheeling SBD or JBS diode, and FIGS. 5A and 5B provide a schematic circuit representation (FIG. 5A) and exemplary layout design (FIG. 5B) of such a switch monolithically formed using multi-finger LTJFETs.

FIGS. 6 and 7 are schematic cross-sectional representations of single-finger normally-off JFET power switches where enhancement-mode low-voltage LTJFETs control high-voltage discrete normally-on depletion-mode VJFETs. FIG. 6 shows a hybrid JFET power switch with a built-in anti-parallel PiN diode, and FIG. 7 shows a JFET power switch comprising an anti-parallel SBD or JBS diode monolithically integrated with a high-voltage VJFET.

An exemplary implementation of the technology described above is shown in FIG. 8. As shown in FIG. 8, a monolithic LTJFET timer circuit drives a built-on-chip low-voltage high-current enhanced-mode LTJFET connected in cascode with a discrete high-voltage normally-on power VJFET.

Although vertical channel multi-finger LTJFETs are preferable in high-power application because of their low specific on-resistance and absence of trapping effects common in wide bandgap semiconductors, alternative JFET structures (e.g., those with a lateral channel) can also be employed to form normally-off power JFET switches. FIGS. 9-17 illustrate various exemplary embodiments of integrated JFET switches built using enhanced and depletion mode Lateral Junction Field-Effect Transistors (LJFETs).

FIG. 9 is a schematic cross-sectional representation with electrical connections of a lateral channel JFET integrated circuit comprising enhanced and depletion mode LJFETs having expitaxially overgrown gates. As shown in FIG. 9, the integrated circuit forms a monolithic inverter circuit. The LJFETs used to form the inverter are built on the wide bandgap semiconductor substrate (1), which can be either: semi-insulating; p-type; or n-type with a p-type buffer layer. As shown in FIG. 9, the integrated circuit comprises buffer (2) and channel (5 a) epitaxially grown n-type layers, as well as implanted source and drain (6 a) regions and expitaxially grown p-type gate regions (7 a). The device structures can be defined using plasma etch and ion implantation. The ohmic contacts (8) to the source, gate, and drain regions can be formed on the same side of the wafer allowing for the use of the device in monolithic integrated circuits.

FIG. 10 is a schematic representation of a pitch of a monolithic normally-off JFET power switch built using enhanced and depletion mode LJFETs with overgrown gate regions. As can be seen from the schematic presentation of electrical connections, the devices are connected in cascode configuration in such a way that the drain of the low-voltage enhanced mode LJFET (referred to as an “ELJFET”) is connected to the source of the higher-voltage depletion mode LJFET (referred to as a “DLJFET”), and the gate of the DLJFET is connected to the source of the control ELJFET.

FIG. 11 shows a schematic cross-section of a hybrid normally-off JFET power switch wherein a low-voltage ELJFET controls a high-voltage discrete normally-on depletion-mode VJFET.

An alternative LJFET structure where source and drain regions are formed in an epitaxially grown n-type layer and gate regions are defined by ion implantation can also be used. Devices of this type are shown in FIGS. 12-17.

FIG. 12 shows is a schematic cross-sectional representation with electrical connections of a monolithic inverter, circuit comprising enhanced and depletion mode implanted-gate LJFETs. As shown, the devices used to form the inverter are built on a wide bandgap semiconductor substrate (1), which can be either: semi-insulating; p-type; or n-type with a p-type buffer layer. As also shown, the device comprises buffer (2), channel (5 b), source and drain (6) epitaxially grown n-type layers, as well as implanted gate (7) regions.

FIG. 13 is a schematic cross-sectional representation of a pitch of a monolithic normally-off JFET power switch built using enhanced and depletion mode implanted-gate LJFETs. As shown in FIG. 13, the drain of the D-mode LJFET is laterally spaced from the gate on the channel layer (5 b) to form a lateral drift region in the device.

FIG. 14 is a schematic cross-sectional representation of a normally-off JFET power switch where an enhancement-mode low-voltage implanted-gate LJFET controls a high-voltage discrete normally-on depletion-mode VJFET.

FIG. 15 is a schematic cross-sectional representation of a monolithic normally-off JFET power switch wherein an enhancement-mode low-voltage dual-gate LJFET controls a high-voltage discrete normally-on depletion-mode VJFET. As shown in FIG. 15, the bottom gate of the LJFET is implanted into drift region (4) before the channel region is grown thereon.

FIG. 16 is a schematic cross-sectional representation of a device as shown in FIG. 3D wherein the bottom gate of the LJFET is implanted into drift region 4 together with guard rings. The guard rings can be used to increase the voltage blocking capability of the switch.

Although FET devices having implanted p-type gates are described above, Schottky gates can also be employed for the fabrication of a normally-off FET power switch. FIG. 17 is a schematic cross-sectional representation of a device as shown in FIG. 16 wherein the implanted p-type top gate of the LJFET and the implanted gate of the discrete normally-on depletion-mode VJFET are replaced with Schottky gates. As shown, the Schottky gate of the discrete normally-on FET also serves as an integrated anti-parallel free-wheeling diode.

FIGS. 18A-18D shows a simulated device structure (FIG. 18A), schematic cross-sectional representation (FIG. 18B) and graphs showing the output DC characteristics (FIGS. 18C and 18D) of a SiC LTJFET integrated switch, where both the EJFET and the DJFET have channel peripheries of 1 cm.

In order to demonstrate feasibility of the above described cascode power switch, a hybrid embodiment of the switch was constructed using discrete non-terminated enhanced and depletion mode vetical JFETs. FIGS. 19A-19D are a photograph (FIG. 19A), a schematic representation (FIG. 19B) and graphs showing measured characteristics (FIGS. 19C and 19D) of a hybrid normally-off, 900 V power switch. As can be seen from FIGS. 19C and 19D, despite relatively high leakage current (I_(D)=330 μA @ V_(DS)=900 V and V_(GS)=0 V) induced by the depletion mode device, the voltage-controlled SiC power switch was controlled by as little as 2.75 V.

The basic function of the switch can be described as follows. At the HIGH control level (e.g., V_(GS)=2.75 V), the enhanced mode transistor (EJFET) is turned on. Between the gate and source of the depletion mode transistor (DJFET) only a small voltage drop occurs, therefore, DJFET is on too. If EJFET is turned off with the LOW control level (V_(GS)=0.25 V) its drain-to-source voltage increases to 40-50V as shown in FIG. 20B. This voltage pinches-off the DJFET.

The specific on-resistance of the integrated switch can be minimized as follows. First, the ratios of pinch-off voltages and channel peripheries of both transistors (e.g., EJFET and DJFET) can be adjusted so that they will have approximately equal on-resistances and neither one will therefore limit the overall current. Second, the device can be constructed such that the gate-to-source breakdown voltage of DJFET is equal or higher than the drain-to-source breakdown voltage of EJFET.

In addition, the finger length of high-current multi-finger LTJFETs can be reduced to keep the resistances of the alteral drain region compatible to the resistance of the vertical n⁺ substrate. FIGS. 21A and 21B are schematic representations of distributed drain resistances of LTJFET (FIG. 21A) and VJFET (FIG. 21B), and graph (FIG. 21C) showing resistance of the lateral drain layer of LTJFET normalized to the resistance of the vertical drain of VJFET as a function of finger length for different dopings of the lateral drain layer. As can be seen from FIG. 21C, for a heavily doped 1-μm thick lateral drain layer (3), the finger length of the LTJFET will preferably not exceed 100 μm in length. The finger length, however, can be increased by increasing the thickness and/or the doping levels of the drain layer (3).

FIGS. 22A-22H illustrate a method of making a device as set forth in FIG. 9. FIG. 22A shows a multi-layer structure comprising a substrate (1), an epitaxially grown p-type layer (2), and an epitaxially grown n-type layer (5 a). An etch mask (10) is positioned on the exposed surface of epitaxially grown n-type layer (5 a) as shown in FIG. 22B. Epitaxially grown n-type layer (5 a) is then selectively etched (12) as shown in FIG. 22B. Etch mask (10) is then removed and ion implantation mask (14) is then placed on the etched surface of epitaxially grown n-type layer (5 a) as shown in FIG. 22D. Ion implantation of n-type dopants through mask (14) results in the formation of highly n-doped regions (6 a) in epitaxially grown n-type layer (5 a) as shown in FIG. 22E. Mask (14) is then removed and a layer of p-type semiconductor material (7 a) is grown on the etched and implanted surface of epitaxially grown n-type layer (5 a) as shown in FIG. 22F. Etch mask (16) is then positioned on the exposed surface of layer (7 a) as shown in FIG. 22G. Etching through mask (16) results in selective removal of layer (7 a) and formation of raised p-type features as also shown in FIG. 22G. Finally, mask (16) is removed and ohmic contacts are formed on exposed surfaces of the raised p-type features and the implanted regions (6 a).

The method as outlined above can also be used, by selecting appropriate masks, to form a structure as shown in FIG. 10.

FIGS. 23A-23H illustrate a method of making a structure as shown in FIG. 12. FIG. 23A shows a substrate (1), an epitaxially grown p-type layer (2) on the substrate (1), and an epitaxially grown n-type layer (5 b) on layer (2). As shown in FIG. 23B, an etch mask (18) is positioned on the exposed surface of layer (5 b). Etching (20) results in selective removal of material from layer (5 b) as shown in FIG. 23C. After removal of mask (18), an n-type epitaxial layer (6) is grown on the etched surface of layer (5 b) as shown in FIG. 23D. Etch mask (22) is positioned on the exposed surface of layer (6) as shown in FIG. 23E and etching (24) results in selective removal of material from layer (6) and exposure of underlying layer (5 b) as shown in FIG. 23F. Mask (22) is then used to selectively implant p-type donors in exposed surface of layer (5 b) to form implanted gate regions (7) as shown in FIG. 23G. Ohmic contacts (8) are then formed on the implanted p-type gate regions (7) to form the gate contacts and on the raised n-type regions (6) to form the source and drain contacts for the device as shown in FIG. 23H.

The method as outlined above can also be used, by selecting appropriate masks, to form a structure as shown in FIG. 13.

FIGS. 24A-24J illustrate a method of making a structure as shown in FIG. 15. FIG. 24A shows an n-type substrate (1 a), an epitaxially grown n-type layer (3 a) on substrate (1 a), and an epitaxially grown n-type layer (4 a) on layer (3 a). An ion implantation mask (26) is also shown on the exposed upper surface of layer (4 a). As shown in FIG. 24B, layer (4 a) is selectively implanted with p-type donor atoms through mask (26) to form gate region (7). After removal of mask (26), an n-type epitaxial layer (5) and an n-type epitaxial layer (6) are successively grown on the implanted surface of layer (4 a) as shown in FIGS. 24C and 24D. Etch mask (30) is then positioned on the exposed surface of layer (6) as shown in FIG. 24D followed by etching (31) through layer (6) and partially through underlying layer (5) (FIG. 24E). Exposed portions of layer (5) are then implanted with p-type donor atoms through mask (30) to form additional gate regions (7) as shown in FIG. 24F. Etch mask (34) is then positioned on the surface of the etched and implanted structure and etching (36) results in selective removal of portions of layer (5) including portions of the p-type implanted gate regions (FIG. 24H). Exposed portions of layer (4 a) are then etched (40) through mask (38) as shown in FIG. 24I. Ohmic contacts (8) are then formed on the etched and implanted structure to form the device as shown in FIG. 24J.

The method as outlined above can also be used to form a structure as shown in FIG. 16.

FIGS. 25A-25D illustrate a method of making a structure as shown in FIG. 17. As shown in FIG. 25A, a structure a shown in FIG. 24E is etched (44) through mask (42) to expose portions of underlying layer (4 a) (FIG. 25B). Schottky contacts (9) are then formed on the etched/implanted structure as shown in FIG. 25C. The formation of ohmic contacts (8) results in the device as shown in FIG. 25D.

Although exemplary embodiments are discussed above, other alternative embodiments are also possible. For example, GaN n-type epitaxial layers can be grown on silicon carbide, sapphire, or silicon substrates to form a starting material stack for the fabrication of the proposed device structure. Alternatively, a substrate material comprising a conducting SiC substrate with a semi-insulating epitaxially grown buffer layer can be used as disclosed in U.S. patent application Ser. No. 10/033,785, filed Jan. 3, 2002 (published as U.S. Patent Publication No. 2002-0149021).

The SiC layers can be formed by doping the layers with donor or acceptor materials using known techniques. Exemplary donor materials include nitrogen and phosphorus. Nitrogen is a preferred donor material. Exemplary acceptor materials for doping SiC include boron and aluminum. Aluminum is preferred acceptor material. The above materials are merely exemplary, however, and any acceptor and donor materials which can be doped into silicon carbide can be used. The doping levels and thicknesses of the various layers of the LTJFETs, LJFETs and VJFETs described herein can be varied to produce a device having desired characteristics for a particular application. Similarly, the dimensions of the various features of the device can also be varied to produce a device having desired characteristics for a particular application.

The SiC layers can be formed by epitaxial growth on a suitable substrate. The layers can be doped during epitaxial growth.

While the foregoing specifications teach the principles of the present invention, with examples provided for the purpose of illustration, it will be appreciated by one skilled in the art from reading this disclosure that various changes in form and detail can be made without departing from the true scope of the invention.

CITED REFERENCES

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1-90. (canceled)
 91. A method comprising: positioning a first mask on a layer of n-type semiconductor material, wherein the layer of n-type semiconductor layer is on a first layer of p-type semiconductor material and the first layer of p-type semiconductor material is on a substrate; selectively etching the layer of n-type semiconductor material through openings in the first mask to form an etched region and a raised region having a sidewall adjacent the etched region; removing the first mask; positioning a second mask on the layer of n-type semiconductor material which masks a portion of the etched region and a portion of the raised region; implanting n-type dopants in the layer of n-type semiconductor material through openings in the mask to form a first non-implanted region over the etched region, a second non-implanted region over the raised region and n-type implanted regions in the layer of n-type semiconductor material; removing the second mask; epitaxially growing a second layer of p-type semiconductor material on the etched and implanted layer of n-type semiconductor material; positioning a third mask on the second layer of p-type semiconductor material which masks a portion of the second layer of p-type semiconductor material over the first non-implanted region and a portion of the second layer of p-type semiconductor material over the second non-implanted region; using the third mask, selectively etching through the second layer of p-type semiconductor material to expose implanted regions in the underlying layer of n-type semiconductor material thereby forming raised features of p-type semiconductor material; removing the third mask; and forming ohmic contacts on the raised features and on the implanted regions in the layer of n-type semiconductor material.
 92. The method of claim 91, wherein the n-type implanted regions have a dopant concentration of 5×10¹⁸ cm⁻³ or greater and a thickness of 0.1 μm or greater.
 93. The method of claim 91, wherein the substrate is a semi-insulating substrate.
 94. The method of claim 91, wherein the layer of n-type semiconductor material has a thickness of 0.2 to 1.5 μm and a dopant concentration, prior to implantation, of 5×10¹⁵ to 2×10¹⁷ cm⁻³.
 95. The method of claim 91, wherein the second layer of p-type semiconductor material is epitaxially grown to a thickness of 0.2 to 1.5 μm and has a doping concentration greater than 5×10¹⁸ cm⁻³.
 96. The method of claim 91, wherein the first layer of p-type semiconductor material has a thickness of 0.1 μm or greater and a dopant concentration of 1×10¹⁵ to 1×10¹⁷ cm⁻³.
 97. A method comprising: positioning a first mask on a first layer of n-type semiconductor material, wherein the first layer of n-type semiconductor layer is on a layer of p-type semiconductor material and the layer of p-type semiconductor material is on a substrate; selectively etching the first layer of n-type semiconductor material through openings in the first mask to form an etched region and a raised region; removing the first mask; epitaxially growing a second layer of n-type semiconductor material on the etched and implanted layer of n-type semiconductor material; positioning a second mask on the second layer of n-type semiconductor material such that openings in the second mask are located over the etched region of the layer of n-type semiconductor material and over the raised region of the layer of n-type semiconductor material; using the second mask, selectively etching through the second layer of n-type semiconductor material to expose the underlying first layer of n-type semiconductor material and to form raised features of n-type semiconductor material; selectively implanting p-type dopants in the first layer of n-type semiconductor material through the openings in the second mask to form p-type implanted regions; removing the second mask; and forming ohmic contacts on exposed surfaces of the raised features of n-type semiconductor material and the p-type implanted regions.
 98. The method of claim 97, wherein the second layer of n-type semiconductor material is more heavily doped that the first layer of n-type semiconductor material.
 99. The method of claim 97, wherein the second layer of n-type semiconductor material has a thickness of 0.2 to 1.5 μm and a dopant concentration greater than 5×10¹⁸ cm⁻³.
 100. The method of claim 97, wherein the first layer of n-type semiconductor material has a thickness of 0.3 to 1.5 μm and a dopant concentration of 5×10¹⁵ to 2×10¹⁷ cm⁻³.
 101. The method of claim 97, wherein the p-type implanted regions have a thickness of 0.1 μm or greater and a dopant concentration greater than 5×10¹⁸ cm⁻³.
 102. A method comprising: positioning a first mask on a first layer of n-type semiconductor material, wherein the first layer is on a second layer of n-type semiconductor material and the second layer is on a substrate; using the first mask, selectively implanting p-type dopants in the first layer to form a p-type implanted region adjacent a non-implanted region in the first layer; removing the first mask; epitaxially growing a third layer of n-type semiconductor material on the first layer; epitaxially growing a fourth layer of n-type semiconductor type material on the third layer; positioning a second mask on the fourth layer; selectively etching through the fourth layer to expose underlying third layer through openings in the second mask thereby forming raised features of n-type semiconductor material over the p-type implanted region of the first layer and one or more raised features of n-type semiconductor material over the non-implanted region of the first layer; implanting p-type dopants in the third layer through openings in the second mask to form p-type implanted regions in the third layer between and adjacent the raised features of n-type semiconductor material; removing the second mask; positioning a third mask which masks the raised features and the area between the raised features over the p-type implanted region of the first layer and which masks the one or more raised features over the non-implanted region of the first layer and areas adjacent thereto; using the third mask, selectively etching through the third layer to expose p-type implanted and non-implanted regions of the underlying first layer thereby forming first and second raised structures, wherein the first raised structure comprises the raised features over the p-type implanted region of the first layer and the p-type implanted region of the third layer therebetween and wherein the second raised structure comprises the one or more raised features over the non-implanted region of the first layer and p-type implanted regions of the third layer adjacent thereto; removing the third mask; positioning a fourth mask covering the first and second raised structures and a region of p-type implanted first layer adjacent the first raised structure; using the fourth mask, selectively etching through the p-type implanted region in the first layer of n-type semiconductor material adjacent to and between the first and second raised structures; removing the fourth mask forming ohmic contacts on exposed surfaces of the raised features of n-type semiconductor material and on exposed p-type implanted regions.
 103. The method of claim 102, wherein the second layer of n-type semiconductor material is more heavily doped that the first layer of n-type semiconductor material.
 104. The method of claim 102, wherein the second layer of n-type semiconductor material has a dopant concentration greater than 5×10¹⁸ cm⁻³ and a thickness of 0.5 to 1 μm.
 105. The method of claim 102, wherein the first layer of n-type semiconductor material has a dopant concentration of 2×10¹⁴ to 2×10¹⁶ cm⁻³ and a thickness of 5 to 350 μm.
 106. The method of claim 102, wherein the p-type implanted region in the first layer has a thickness of 0.1 μm or greater and a dopant concentration or 5×10¹⁸ cm⁻³ or greater.
 107. The method of claim 102, wherein the p-type implanted regions in the third layer have a thickness of 0.1 μm or greater and a dopant concentration or 5×10¹⁸ cm⁻³ or greater.
 108. The method of claim 102, wherein the third layer of n-type semiconductor material has a dopant concentration of 5×10¹⁵ to 5×10¹⁷ cm⁻³ and a thickness of 0.2 to 1.5 μm.
 109. The method of claim 102, wherein the fourth layer of n-type semiconductor material has a dopant concentration greater than 5×10¹⁸ cm⁻³ and a thickness of 0.2 to 1.5 μm.
 110. The method of claim 102, wherein the n-type substrate has a dopant concentration greater than 1×10⁸ cm⁻³.
 111. A method comprising: positioning a first mask on a first layer of n-type semiconductor material, wherein the first layer is on a second layer of n-type semiconductor material and the second layer is on a substrate; using the first mask, selectively implanting p-type dopants in the first layer of n-type semiconductor material to form a p-type implanted region adjacent a non-implanted region in the first layer; removing the first mask; epitaxially growing a third layer of n-type semiconductor material on the first layer; epitaxially growing a fourth layer of n-type semiconductor type material on the third layer; positioning a second mask on the fourth layer; selectively etching through the fourth layer to expose underlying third layer through openings in the second mask thereby forming raised features of n-type semiconductor material over the p-type implanted region of the first layer and one or more raised features of n-type semiconductor material over the non-implanted region of the first layer; removing the second mask; positioning a third mask which masks the raised features and the area between the raised features over the p-type implanted region of the first layer and which masks the raised feature over the non-implanted region of the first layer; using the third mask, selectively etching through the third layer to expose p-type implanted and non-implanted regions of the underlying first layer thereby forming first and second raised structures, the first raised structure comprising the raised features over the p-type implanted region of the first layer and the region of the third layer therebetween and the second raised structure comprising the raised feature over the non-implanted region of the first layer, the second raised structure having sidewalls; removing the third mask; forming ohmic contacts on exposed surfaces of the raised features of n-type semiconductor material and on the exposed p-type implanted region of the first layer; and forming Schottky contacts on the third layer between the raised features over the p-type implanted region, on the non-implanted portion of the first layer adjacent the second raised structure and on material of the third layer on the sidewalls of the second raised structure.
 112. The method of claim 111, wherein the second layer of n-type semiconductor material is more heavily doped that the first layer of n-type semiconductor material.
 113. The method of claim 111, wherein the second layer of n-type semiconductor material has a dopant concentration greater than 5×10¹⁸ cm⁻³ and a thickness of 0.5 to 1 μm.
 114. The method of claim 111, wherein the first layer of n-type semiconductor material has a dopant concentration of 2×10¹⁴ to 2×10¹⁶ cm⁻³ and a thickness of 5 to 350 μm.
 115. The method of claim 111, wherein the p-type implanted region in the first layer has a thickness of 0.1 μm or greater and a dopant concentration or 5×10¹⁸ cm⁻³ or greater.
 116. The method of claim 111, wherein the third layer of n-type semiconductor material has a dopant concentration of 5×10¹⁵ to 5×10¹⁷ cm⁻³ and a thickness of 0.2 to 1.5 μm.
 117. The method of claim 111, wherein the fourth layer of n-type semiconductor material has a dopant concentration greater than 5×10¹⁸ cm⁻³ and a thickness of 0.2 to 1.5 μm.
 118. The method of claim 111, wherein the n-type substrate has a dopant concentration greater than 1×10¹⁸ cm⁻³. 